-- a 5 bit up/down counter with reset. The counter counts to 31
-- and then pauses and counts down till it reaches 0.
-- where it pauses and counts up again.
-- This can be used for a triangle wave generator
-- using integers
-- Author C.J. Kikkert Tutorial 2 EE4306, 18 August 2005

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity UpDown is
port( 	clk, Rst: in std_logic;	--Inputs and Outputs to the circuit
	Up: inout std_logic;
	Count: inout integer range 0 to 31);
end;

architecture UpDown_arch of UpDown is
begin
	process
	begin
		wait until rising_edge(clk);
		if (Rst = '0' ) then			-- Reset pressed SW1
			Count <= 0;					-- Reset Counter to zero
			Up <= '1';
		elsif ( Up ='1') then		-- Up Counting
			if (Count = 31) then 
			--note (Count = 31) uses less resources that (Count <31)
				Count <= Count; 		-- Hold the value
				Up <= '0';				-- Count Down next
			else
				Count <= Count + 1;	--Increment Counter
				Up <= Up; 				-- Hold the value
			end if;	
		else
			if (Count = 0) then		-- Down Counting
				Count <= Count; 		-- Hold the value
				Up <= '1';				-- Count Up next
			else
				Count <= Count - 1;	--Decrement Counter
				Up <= Up; 				-- Hold the value
			end if;
		end if;
	end process;	
end UpDown_arch;