-- Module for a 4 bit to seven segment display decoder
-- Author C. J. Kikkert, 16 Aug 2004 Mods 13 Aug 2008 for DAC output
-- Connect DAC board to pins 14 to 18 using ribbon cable
library ieee;
use ieee.std_logic_1164.all; 

entity SevenSeg is
	Port (Hexin: in std_logic_vector (3 downto 0);
		SevSegOut: out std_logic_vector (6 downto 0));
end;

architecture SevenSeg_arch of SevenSeg is
begin
	process(Hexin)
	begin
		Lab0: case Hexin is
		-- need to have inverse of output coded here since the
		-- board displays include inverters. 
      	when X"0" => SevSegOut <= "0000001";	--0
      	when X"1" => SevSegOut <= "1001111";	--1
      	when X"2" => SevSegOut <= "0010010";	--2
      	when X"3" => SevSegOut <= "0000110";	--3
      	when X"4" => SevSegOut <= "1001100";	--4
      	when X"5" => SevSegOut <= "0100100";	--5
      	when X"6" => SevSegOut <= "0100000";	--6
      	when X"7" => SevSegOut <= "0001111";	--7
      	when X"8" => SevSegOut <= "0000000";	--8
      	when X"9" => SevSegOut <= "0000100";	--9
      	when X"A" => SevSegOut <= "0001000";	--A
      	when X"B" => SevSegOut <= "1100000";	--b
      	when X"C" => SevSegOut <= "0110001";	--C
      	when X"D" => SevSegOut <= "1000010";	--d
			when X"E" => SevSegOut <= "0110000";	--E
      	when others => SevSegOut <= "0111000";	--F
      end case Lab0;
	end process; 
end SevenSeg_arch;

-- end of 4 bit to seven segment display decoder module

-- a 5 bit up/down counter with reset. The counter counts to 31
-- and then pauses and counts down till it reaches 0.
-- where it pauses and counts up again.
-- This can be used for a triangle wave generator
-- using std_logic_vectors
-- Author C.J. Kikkert Tutorial 2 EE4306, 18 August 2005


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity UpDown is
port( 	clk, Rst: in std_logic;	--Inputs and Outputs to the circuit
	Up: inout std_logic;
	Count: inout std_logic_vector (4 downto 0);	-- Counter output for driving DAC
	SevSeg1: out std_logic_vector (6 downto 0);	-- Seven segment display Digit 3
	SevSeg0: out std_logic_vector (6 downto 0)	-- Seven segment display MS Digit
--	Count: inout std_logic_vector(4 downto 0)
	);
	attribute loc : string;
	attribute loc of clk:signal is "P11"; 
	attribute loc of Count:signal is "P14, P15, P16, P17, P18" ;
	attribute loc of SevSeg1:signal is "P24, P25, P26, P27, P28, P29, P30" ;
	attribute loc of SevSeg0:signal is "P36, P37, P38, P39, P40, P41, P42" ;	--pin allocation of MS display
end;

architecture UpDown_arch of UpDown is
	component SevenSeg
		port (Hexin: in std_logic_vector;
		SevSegOut : out std_logic_vector);
	end component;
--	signal	Count: std_logic_vector (7 downto 0);			-- 8 bit counter for all bits.

begin
	D0: SevenSeg port map (Count(3 downto 0), SevSeg0);	-- Seven Segment Display LS Digit
	D1: SevenSeg port map ("000" & Count(4), SevSeg1);	-- Seven Segment Display Digit 2

	process
	begin
		wait until rising_edge(clk);
		if (Rst = '0' ) then			-- Reset pressed SW1
			Count <= "00000";		-- Reset Counter to zero
		elsif ( Up ='1') then		-- Up Counting
			if (Count = "11111") then
				Count <= Count; 		-- Hold the value
				Up <= '0';				-- Count Down next
			else
				Count <= Count + "00001";	--Increment Counter
				Up <= Up; 				-- Hold the value
			end if;	
		else
			if (Count = "00000") then
				Count <= Count; 		-- Hold the value
				Up <= '1';				-- Count Up next
			else
				Count <= Count - "00001";	--Decrement Counter
				Up <= Up; 				-- Hold the value
			end if;
		end if;
	end process;
	
	
end UpDown_arch;