library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; --note the different library required for vector addition

entity VarDivider is
	port (Clk ,Rset: in STD_LOGIC;
		MaxNo : in std_logic_vector (5 downto 0);
	Count : inout std_logic_vector (6 downto 0);

		Zout : inout STD_LOGIC);
	attribute loc: string;
	attribute loc of Clk: signal is "p11";
	attribute loc of Rset: signal is "p9";	--Switch 1 on M4A5 Development Board
--	attribute loc of Rset: signal is "p35";	--Reset on ispLSI2032 Boards 
	attribute loc of MaxNo: signal is "p30 p29 p28 p27 p26 p25";	
	attribute loc of Zout: signal is "p31";

end;

architecture VarDivider_Arch of VarDivider is
--	signal 	Count : std_logic_vector (6 downto 0);
	signal CountVal: std_logic_vector (6 downto 0);
begin
	process (clk)
	begin
		if rising_edge (Clk) then
			if (Rset = '0') then
			Count <= "0000000";
			elsif (Count = CountVal) then
					Count <= "0000000";
--					Zout <= not Zout;	--if want even mark spoace ratio, but get half the output freq.
				else
					Count <= Count + "0000001";
			end if;
		end if;
	end process;
--Note in the above process Count is always avaluated and only once

	process (MaxNo)
	Begin
--	CountVal(5 downto 0) <= MaxNo;
--	CountVal(6) <= '1';
	Countval <= '1'& MaxNo; --This is an alternate to the 2 lines above
	end process;

	process (Count)
	begin
			Zout <= Count(6);
	end process;

end VarDivider_Arch;